The present invention relates to semiconductor devices and methods of manufacturing the same and, more particularly, to field effect transistors (FETs) and methods of manufacturing the same.
As the number of applications of semiconductor devices has increased, demand for highly integrated and/or high-speed semiconductor devices has increased. As the integration of semiconductor devices has increased, design rule has tended to decrease, e.g., channel lengths and channel widths of MOS (metal-oxide-semiconductor) transistors have decreased.
When channel length decreases, a short channel effect can occur, and when the channel width decreases, a narrow width effect can occur. Short channel effect refers to a breakdown of a channel region when a potential is applied between source and drain regions. Narrow channel effect refers to an increase in a threshold voltage due to a reduction of the width of a channel region. Various different structures for MOS transistors have been proposed to reduce short channel effect and narrow width effect.
An example of a proposed MOSFET is a MOS transistor having a fin structure as disclosed in U.S. Pat. No. 6,413,802, issued to Chenming Hu, entitled “FinFET Transistor Structures Having a Double Gate Channel Extending Vertically from a Substrate and Methods of Manufacture”. Another example is a MOS transistor having a fully depleted lean-channel transistor (DELTA) structure as disclosed in U.S. Pat. No. 4,996,574, issued to Shirasaki, entitled “MIS Transistor Structure for Increasing Conductance between Source and Drain Regions”. Another example is a MOS transistor having a Gate All Around (GAA) structure as disclosed in U.S. Pat. No. 6,605,847, issued to Kim et al., entitled “Semiconductor Device Having Gate All Around Type Transistor and Method of Forming the Same”.
The aforementioned MOS transistors each have merits and demerits, some of which are described in U.S. Patent Publication No. 20040063286, entitled “Field Effect Transistors Having Multiple Stacked Channels”, assigned to the assignee of the present application. U.S. Patent Publication No. 20040063286, incorporated by reference herein in its entirety, proposes a MOS transistor having a structure that solves the demerits of the proposed MOS transistor examples. The MOS transistor has a multi bridge channel (MBC) structure in which multiple channels are vertically stacked and separated from one another. Because a MOS transistor having such an MBC structure may have a reduced area occupied by source and drain regions, such a MOS transistor may be favorable for high integration. Because such a MOS transistor may maintain a substantially uniform source and drain junction capacitance regardless of a location of a channel, such a MOS transistor may be used to manufacture high-speed and highly reliable semiconductor devices.
The above-described MOS transistors having a fin channel structure, a DELTA channel structure, a GAA channel structure, and an MBC channel structure may have limits with regard to high-speed operations. In a MOS transistor having an MBC structure, a cross-section of a channel layer surrounded by a gate electrode typically has the form of a rectangle having a greater horizontal extent than vertical extent. Due to such a cross-section, a higher voltage may be applied to the channel layer by the gate electrode in the vertical direction than in the horizontal direction. When different voltages are applied to the channel layer by the gate electrode in different directions, carriers (e.g., electrons) flowing through the channel layer generally go upward or downward instead of in a straight line. Accordingly, the probability that the carriers will impact with particles constituting the channel layer generally increases. Scattering occurs due to such impacts and, consequently, a speed of electrons flowing to a source and drain region via the channel layer may decrease. Thus, a semiconductor device including the conventional MOS transistor having the MBC structure may not operate desirably at high speed. This problem may also occur in MOS transistors having the other aforementioned channel structures.
In addition, there may be a limit to the number of spaced channel layers that may be included in a conventional MOS transistor having an MBC structure due to limits on etching depth that can be achieved during dry etching. The limit to the number of channel layers may prevent improvement of the performance and reliability of an MBC MOS transistor.